With the ever increasing demand for user data, there is also an ongoing demand for higher modulation. High modulation, however, typically requires shorter burst durations and correspondingly shorter decoder processing time. Conventional decoders employ single port memory architectures in order to reduce size and costs. Single port memory architectures only facilitate read or write access during a given CPU or bus clock cycle. Read and write operations cannot be simultaneously performed in the same clock cycle. Consequently, two clock cycles are required to complete operations that read and update (write) to memory such as those performed by low density parity check (LDPC) decoders.
Various hardware changes can be made to provide decoder configurations capable of meeting the demands of higher modulation. Such configurations, however, are typically accomplished with an increase in size and cost of the resulting device. For example, one or more single port memory devices can be replaced with dual port memory devices in order to facilitate simultaneous access to both read and write operations in one clock cycle. Dual port memory devices are physically larger (e.g., 2-3 times), have increased power consumption, and are more expensive than corresponding single port memory devices. Thus, while capable of meeting the modulation and processing demands, dual access memory devices increase the size and cost of the decoder. Furthermore, such increases can prohibit use of the decoder in devices with strict space limitations.
Another configuration for meeting the demands of higher modulation requires increasing the clock speed of the decoder. Such a configuration allows the use of existing single port memory devices and does not require changes to the decoder's processing engines. Increasing the clock speed of the decoder, however, will also increase the dynamic power consumption and possibly require redesigning some of the decoder logics. It will also be difficult to meet the timing constraints at a very high clock speed.
The number of processing engines in the decoder can also be increased together with a proportionate increase in the width of the memory device. Such configurations, however, will typically require an increase in logic size and high parallelism, which ultimately makes routing more difficult. Furthermore, the increased width of the memory device will occupy more space. Various combinations of the foregoing configurations can also be applied. However, the same disadvantages will persist.
Based on the foregoing, there is a need for an approach for significantly increasing decoder throughput to accommodate increased modulations and reduced burst durations, without significant increases in area and/or power.